The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
NVM, for example NAND-type Flash in a solid state drive (SSD), often stores low density parity check (LDPC) encoded data. The data may be stored in multi-bit cells organized into pages of the memory. The data may be retrieved according to either a hard read or a soft read as long as the center read reference voltage used to read the data from the cells in the page is correctly positioned. If the center read reference voltage is not correctly positioned, then the raw bit error rate (RBER) may increase and this can lead to LDPC decoding failure. This decoding failure may be especially prevalent for hard data reads. Additionally, if the read reference voltage is not correctly chosen, then confidence information provided by soft bit reads may not be optimized.
To overcome this problem, prior solutions have proposed a moving read reference (MRR) which consists of moving the center read reference on an ad-hoc basis. Specifically, prior solutions have read data from the NVM using hard bit reads, and then used algebraic error correcting codes like Bose-Chaudhuri-Hocquenghem (BCH) codes to attempt to reposition the center read reference voltage. However, the use of BCH codes may not be desirable in certain circumstances. Additionally, the use of BCH codes may preclude the ability to use soft bit reads and obtain confidence data for one or more cell values.